Pic32 Instruction timings

Created Fri, 02 Dec 2011 06:17:33 +0000 by luxeomni

luxeomni

Fri, 02 Dec 2011 06:17:33 +0000

for a pic32-based chipkit with 80Mhz crystal, what is the timing for a single instruction?

I think the mips core has a 5 stage pipeline, does that means that when the pipelines are all full, the time between each instruction is reduced to 12.5 ns?

WestfW

Fri, 02 Dec 2011 06:49:01 +0000

Yep. Unless you do things that stall or flush the pipeline, you move along at one instruction per clock. Now, the list of things that would stall the pipeline on a MIPS architecture machine used to be pretty long (including things like using a register as a source immediately after using it as a destination), and I'm not sure how that effects the Microchip implementation of the M4K version of the CPU.

"Easy" determinism seems to be one of the things that many RISC CPUs give up (complicated caching and prefetching strategies are a common complication as well. The ST talk on their F4 series ARMs includes hand waving like "at 125MHz, the flash requires 5 wait states, but we fetch 6 words at a time so this hardly ever causes a delay. Hmph.) Not that modern high-end CISC cpus are any better. RAM/FLASH access speed has NOT kept up with cpu clock rates.